IS61DDPB21M18A sram
18mb ddr-iip(burst 2) cio synchronous sram.18mb ddr-iip(burst 2) cio synchronous sram.
DESCRIPTION
* 512Kx36 and 1Mx18 configuration available.
* On-chip Delay-Locked Loop (DLL) for wide data valid window.
* Common I/O read and write ports.
where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system o.
* 512Kx36 and 1Mx18 configuration available.
* On-chip Delay-Locked Loop (DLL) for wide data valid window.
* Common I/O read and write ports.
* Synchronous pipeline read with self-timed late write operation.
* Double Data Rate (D.
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